1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, a wafer and a reticle. More particularly, the present invention relates to a semiconductor device manufacturing method using photolithography. The invention also pertains to a wafer and reticle used in manufacture of semiconductor devices.
2. Description of the Related Art
In manufacture of semiconductor devices, a number of chips (semiconductor devices) are formed on one wafer. These chips are cut into individual dice. Among the diced chips, only nondefective chips are conveyed to a subsequent packaging step. Before the dicing, there is normally inspected whether or not each chip formed on the wafer or the wafer itself is a nondefective product. For a method for performing quality determination of chips or a wafer before the dicing, there is disclosed a method for measuring electric characteristics of a part or all of the chips formed on the wafer to perform the quality determination or a method for measuring electric characteristics of a monitor element or monitor circuit (referred to as a “monitor element/circuit”) previously formed with chips on the wafer to perform the quality determination based on the measurement results.
In connection with the determination method like this, there is conventionally proposed a measuring method of the electric characteristics (see, Japanese Unexamined Patent Publication No. Hei 10-50777). That is, when bringing a probe needle of a tester into contact with an electric pad on a chip to measure the electric characteristics, in order to prevent the chip from being damaged due to deviation in a contact position of the probe needle or due to biting of the probe needle into the electric pad, the contact position or biting depth of the prove needle is adjusted before the contact of the prove needle with the electric pad while bringing the probe needle into contact with a monitor pad previously formed apart from the electric pad.
In addition, there is also proposed a method for forming a monitor element/circuit (see, Japanese Unexamined Patent Publication No. 2002-280293), in which a first reticle having formed thereon a chip pattern and a second reticle having formed thereon a pattern for a monitor element or for a monitor circuit (referred to as a “monitor element/circuit pattern) are used in an exposure step. In this proposal, the monitor element/circuit pattern of the second reticle is formed on a resist in an area served as a dicing line of a wafer. Further, after exposing a shot position through the first reticle, the resulting shot position is exposed through the second reticle. As a result, the first reticle gives shade to an area where the monitor element/circuit pattern is exposed later through the second reticle, and the second reticle gives shade to an area where the chip pattern is already exposed through the first reticle. That is, after exposing all of the shot positions through the first reticle, these resulting shot positions are alternately exposed through the second reticle. Thus, the chip pattern is formed on the resist of the wafer as well as the monitor element/circuit pattern is formed on the resist in the area served as the dicing line of the wafer.
However, in the quality determination of a wafer before dicing, the above-described method for measuring the respective electric characteristics of a part or all of the chips formed on the wafer has a problem that measurement is complicated, a long measuring time is required or an expensive measuring device is required. Further, the method has a problem that in a wafer state before dicing, measurement using a high frequency or measurement using a large current may be hardly performed on each chip.
On the contrary, the method for performing the quality determination of the wafer by measuring the electric characteristics of the monitor element/circuit formed with the chips has the following advantages. That is, the electric characteristics of the monitor element/circuit like this are easily measured normally. Further, the monitor element/circuit has a construction simpler than that of the chips. Therefore, this measurement method can be simply performed at low cost as compared with the method for measuring the chip itself.
However, when using this method, a monitor element/circuit is formed on a wafer in addition to chips originally required. Therefore, in order to obtain as many chips as possible from one wafer, an arrangement of the monitor element/circuit on the wafer must be taken notice of. For a method for arranging the monitor element/circuit on the wafer, the following methods are considered in addition to the above-described method for arranging the monitor element/circuit on a dicing line of the wafer, namely, between chips on the wafer. That is, a method for forming a part of chips as the monitor element/circuit, a method for installing at a plurality of positions of the wafer a block having formed thereon the monitor element/circuit, and a method for forming the monitor element/circuit within a chip product are considered.
However, also the method for thus performing quality determination by using the monitor element/circuit has the following problems.
For example, when measuring the electric characteristics of a part or all of the monitor elements/circuits appropriately arranged on the wafer as described above and performing the quality determination of the wafer based on the obtained measurement results, the measurement of as many monitor elements/circuits as possible which are formed in various areas on the wafer must be performed in order to increase determination accuracy. However, when measuring the electric characteristics of a number of monitor elements/circuits, a measuring time of course increases, for all that the measurement of the monitor element/circuit is relatively easy and the construction thereof is simple as compared with that of chips.
Further, when forming a number of the monitor elements/circuits on one wafer, depending on the construction or arrangement of the monitor elements/circuits, an area usable for chips may be reduced to result in reduction of the number of chips. This problem may be avoided by forming the monitor element/circuit on the dicing line as in the above-described example. However, when manufacturing a reticle for forming the monitor element/circuit apart from a reticle for forming a chip, the number of reticles increases. As a result, increase in a manufacturing cost of reticles and increase in the number of manufacturing steps thereof are induced to thereby finally increase in the chip cost.